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LP5521
SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
OPERATION MODE REGISTER (OP MODE)
Address 01H
Reset value 00H
Table 21. OP Mode Register
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7
6
5
R_MODE[1]
4
R_MODE[0]
3
G_MODE[1]
2
G_MODE[0]
1
B_MODE[1]
0
B_MODE[0]
Name
Bit
Access
Active
Description
R channel operation mode
00b = Disabled
R_MODE
5:4
R/W
01b = Load program to SRAM, reset R channel PC
10b = Run program defined by R_EXEC
11b = Direct control
G channel operation mode
00b = Disabled
G_MODE
3:2
R/W
01b = Load program to SRAM, reset G channel PC
10b = Run program defined by G_EXEC
11b = Direct control
B channel operation mode
00b = Disabled
B_MODE
1:0
R/W
01b = Load program to SRAM, reset B channel PC
10b = Run program defined by B_EXEC
11b = Direct control
MODE registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes to OP_MODE register
(01H) need to be longer than 153 μ s (typ).
R CHANNEL PWM CONTROL (R_PWM)
Address 02H
Reset value 00H
Table 22. R PWM Register
7
6
5
4
3
2
1
0
R_PWM[7:0]
Name
R_PWM
Bit
7:0
Access
R/W
Active
Description
R Channel PWM value during direct control operation mode
32
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